Advanced Computer Architecture: 10th Annual Conference, ACA by Junjie Wu, Haibo Chen, Xingwei Wang

By Junjie Wu, Haibo Chen, Xingwei Wang

This e-book constitutes the refereed complaints of the tenth Annual convention on complicated desktop structure, ACA 2014, held in Shenyang, China, in August 2014. the nineteen revised complete papers awarded have been conscientiously reviewed and chosen from a hundred and fifteen submissions. The papers are geared up in topical sections on processors and circuits; excessive functionality computing; GPUs and accelerators; cloud and knowledge facilities; strength and reliability; intelligence computing and cellular computing.

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Additional resources for Advanced Computer Architecture: 10th Annual Conference, ACA 2014, Shenyang, China, August 23-24, 2014. Proceedings

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To exploit the data parallelism, we can copy several ACRPs which combine reconfigurable architecture with SIMD processing. Fig. 1. 1 illustrates a CGRA with two ACRPs that consists of 6 SPEs and 2 CFUs. 6 SPEs are organized into a linear structure. Every SPE can communicate with the other 5 SPEs. The linear structure is best for the pipelined stream-based application. But the drawback is not suitable for mapping the 2D data processing application and the branch code. g. DSP domain kernels are mostly stream-based.

In Section 5, a specific MultiFPGA verification platform is introduced to conduct the experiment simulation and provides the experiment result of leon3, a SoC design based on SPARC processor. Section 6 is for the summary. 2 Partition Flow This paper proposes a partition method of the SoC design serving the Multi-FPGA verification platform. It divides the SoC design into several parts, and then properly maps them into corresponding FPGA chips on the platform. A given SoC design consists of a number of modules and sub-modules described by Verilog or VHDL, which are organized in a hierarchical way.

Liu, and S. Li References 1. : Coarse Grained Reconfigurable Array: Architecture and Application Mapping. IPSJ Transactions on System LSI Design Methodology 4, 31–46 (2011) 2. : Reconfigurable Computing: a Survey of System and Software. ACM Computing Surveys 34(2), 171–210 (2002) 3. : PipeRench: A Coprocessor for Streaming Multimedia Acceleration. In: ISCA (1999) 4. : Mapping applications to the RaPiD configurable architecture. In: Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, April 16-18, p.

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